1. Field of the Invention
The present invention relates to an A/D converter, a solid-state image capturing apparatus, and an electronic information device, and more particularly, to an A/D converter for converting an analog signal to digital data, a solid-state image capturing apparatus including the A/D converter, and an electronic information device including the solid-state image capturing apparatus used therein. The present invention is on the basis of the underlying technology of column-parallel A/D converters, in which a sample hold section and a comparing section are arranged for each column, and which are used for CCD and CMOS image sensors, near-infrared and far infrared image sensors and the like, in which an element for converting energy into an electron, including a photoelectric conversion element, is defined to be one unit pixel and the plurality of pixels are arranged in rows and columns.
2. Description of the Related Art
In solid-state image capturing apparatuses including recent CMOS image sensors, a complicated analog circuit and digital circuit as well as a signal processing unit can be equipped on a CMOS image sensor chip owing to the merging of a CMOS logic process and an image sensor process. Further, some solid-state image capturing apparatuses include an A/D converter equipped on a sensor chip.
The architecture of A/D converters particularly used in solid-state image capturing apparatuses includes the configuration of column-parallel A/D converters.
Column-parallel A/D converters are the kind of A/D converters in which, substantial parts (e.g., a sample hold section and a comparing section) of the A/D converters are provided for each column of solid-state image capturing elements (referred to as “pixels” hereinafter) that are arranged in rows and columns. Such A/D converters are advantageous in that they can reduce a conversion rate to a read out rate for one row to reduce its overall power consumption, and that it is easy to increase the read out rate.
Among such column-parallel A/D converters, those with a system of using a ramp wave signal are commonly used. In a case of a resolution of 10 bit accuracy, A/D converters with this system use a system, in which the level of a ramp wave signal is incrementally increased (or decreased) at a 1024 step, and simultaneously count-up (or count-down) is performed by a counter circuit to store a counter value at the time when the output of a comparator is reversed, in a digital memory as digital pixel data of an analog pixel signal, the comparator being for comparing a ramp wave signal level with a pixel signal level.
FIG. 11 is a system configuration diagram of a solid-state image capturing apparatus, such as a CMOS image sensor, represented in Reference 1.
A solid-state image capturing apparatus 200a illustrated in FIG. 11 includes: a plurality of pixels 200 arranged in rows and columns; a vertical decoder circuit 201 for selecting each pixel row; a sample hold circuit and comparing circuit section 4A (also abbreviated as SHC circuit section, hereinafter) for sample holding an analog pixel signal from each pixel column and comparing the signal with a ramp waveform; and a ramp wave generating circuit 202 for generating the ramp waveform. The solid-state image capturing apparatus 200a further includes: a counter circuit 203 for generating an N-bit count value; a digital memory circuit (N-bit) 206 for receiving the N-bit count value and storing the N-bit count value as digital pixel data corresponding to the analog pixel signal described above in accordance with a comparison output from the SHC circuit section 4A; and a horizontal decoder circuit 204 for controlling the digital memory circuit 206 so that digital pixel data stored in each digital memory circuit 206 is successively output.
In addition, FIG. 12 is a diagram describing a column-parallel A/D converter with a conventional technique, which is included in the aforementioned solid-state image capturing apparatus. FIG. 12 illustrates a sample hold circuit and comparison circuit section consisting of capacitances and switches, in the column-parallel A/D converter, along with a pixel circuit constituting a pixel.
One of the inputs to the SHC circuit section 4A is an input signal Vpix from the pixels, and another input is an output signal Vr from the ramp wave generating circuit 202. The ramp wave generating circuit 202 is a circuit for generating a ramp wave to be compared with a difference voltage ΔV between a reset level Vrst and a signal level Vsig, which varies in accordance with the amount of light.
In addition, the pixel 200 is constituted of a pixel circuit 4B. The pixel circuit 4B includes: a photodiode PD for photoelectrically converting incident light; an electric charge accumulating section (floating diffusion) FD for accumulating a signal charge obtained by the photoelectric conversion by the photodiode PD; a transfer transistor Tt for transferring the signal charge from the photodiode PD to the electric charge accumulating section FD; a reset transistor Tr connected between a power source VD and the electric charge accumulating section FD for resetting an electric potential of the electric charge accumulating section FD to a source voltage; an amplifying transistor Ta for amplifying the electric potential of the electric charge accumulating section FD; and a selecting transistor Ts connected between the amplifying transistor Ta and a read out signal line L (also referred to as a pixel signal line, hereinafter) for selecting a pixel. A gate of the reset transistor Tr is input a pixel reset signal RST, a gate of the transfer transistor Tt is input a transfer signal TX, and a gate of the selecting transistor Ts is input a horizontal line selecting signal SEL.
The read out signal line L is provided for each pixel column, and is connected to a constant current source 403. In addition, an analog pixel signal being read by the read out signal line L is supplied to the SHC circuit section 4A functioning as a sample hold circuit and a comparing circuit.
As illustrated in FIG. 12, the SHC circuit section 4A includes: a switch (SW1) 401a connected between a first node N41 and the read out signal line L in the SHC circuit section 4A; a first capacitance element (C1) 402a connected between the first node N41 and a second node N42 in the circuit section; a second switch (SW2) 401b and a second capacitance element (C2) 402b connected in series between the first node N41 and a ramp waveform input node Nr; a comparing circuit 400 connected between the second node N42 and an output node (CPOUT) Ncp; and a third switch (SW3) 401c connected in parallel with the comparing circuit 400. The first to third switches 401a to 401c are controlled to be turned on and off by control signals SW1 to SW3.
The SHC circuit section 4A herein includes a sample hold circuit 4A1 and a comparing circuit 4A2. The sample hold circuit 4A1 is constituted of the two switches 401a and 401b as well as the two capacitance elements 402a and 402b. In addition, the comparing section 4A2 is constituted of the comparing circuit 400 and the third switch 401c. 
In the solid-state image capturing apparatus 200a, in addition, the SHC circuit section 4A, the digital memory circuit 206, the counter circuit 203; and the ramp wave generating circuit 202 constitute the A/D converter 220a. 
It is noted herein that the first to third switches (SW1 to SW3) 401a to 401c are controlled by the control signals SW1 to SW3 and these control signals are supplied from a controlling section 210 together with a pixel driving signal, for explanatory reasons.
Next, the operation will be described.
FIG. 13 is a diagram illustrating a level change in respective driving signals SEL, RST and TX for driving pixels; a level change in respective control signals SW1 to SW3 for controlling the SHC circuit section (sample hold circuit and comparing circuit) 4A; and a voltage change of the input signal Vpix from the pixels.
First, at a time t1, the horizontal line selecting signal SEL is turned on, the horizontal line selecting signal SEL being a pixel driving signal, and simultaneously, the pixel reset signal RST is turned on. As a result, the electric potential level of the floating diffusion FD of a pixel is pulled up to the pixel power source VD, and simultaneously, the voltage of the pixel signal Vpix, that is, the voltage of the read out signal line L connected to the selected pixel, is also increased.
Next, at a time t2, the switch 401a, for controlling the input of the pixel signal Vpix to the sample hold circuit, and the auto-zero switch 401c of the comparing circuit are turned on by the respective control signals SW1 and SW3. The voltage level of the pixel signal Vpix is slightly decreased owing to the influence of feedthrough upon turning on these switches.
At a time t3, the pixel reset signal RST is turned off, so that the voltage of the pixel signal Vpix is settled to the reset level Vrst for the pixel by the first sampling capacitance 402a (capacitance value C1) in the sample hold circuit 4A1, an additional capacitance of the readout signal line L, and an amplification operation of a source follower circuit, which is constituted of a transistor and a constant current source in the pixel.
At a time t4, the auto-zero switch 401c of the comparing circuit is turned off, so that a voltage difference between the reset level Vrst for the pixel and a reverse level Vth for the comparing circuit is retained in the first sampling capacitance 402a. Herein, the reverse level Vth for the comparing circuit is a threshold voltage of the comparing circuit.
Next, at a time t5, the transfer gate (transfer transistor) Tt of the pixel is turned on, so that an electric charge is transferred from the photodiode PD to the floating diffusion FD, and the voltage of the floating diffusion FD is decreased. However, during a dark period as illustrated in FIG. 13, the voltage of the floating diffusion FD is increased owing to capacitance coupling of the transfer gate (the gate of the transfer transistor) and the floating diffusion FD, and the voltage of the pixel signal Vpix is increased simultaneously.
At a time t6, the transfer gate (transfer transistor) Tr is turned off, so that the voltage of the pixel signal Vpix is decreased. At a time t7, the switch 401b is turned on, the switch 401b being for controlling the input of the ramp wave signal Vr of the sample hold circuit 4A1, so that the voltage of a terminal Nb′ is decreased and the voltage of the pixel signal Vpix is decreased simultaneously, the terminal Nb′ being one terminal of the second sampling capacitance 402b, which is connected to the switch 401b. 
Thereafter, as similar to the aforementioned reset sampling period Trs, the voltage of the pixel signal Vpix is settled to the signal level Vsig by a capacitance value C2 of the second sampling capacitance 402b, an additional capacitance of the read out signal line L, and an amplification operation of a source follower circuit, which is constituted of a transistor and a constant current source in the pixel.
At a time t8, the switch 401a is turned off, the switch 401a controlling the input of the pixel signal Vpix to the sample hold circuit, so that the second sampling capacitance 402b is retained a voltage difference between the pixel signal level Vsig and an initial level Vr0 of the ramp wave.
Finally, at a time t9, the horizontal line selecting signal SEL is turnedoff, the horizontal line selecting signal SEL being a pixel driving signal, so that the pixel signal Vpix is increased to return to the initial voltage level.
At this stage, an input voltage Vin of the comparing circuit 400 (e.g., an inverter) is observed to be Vin=Vrmp+(Vsig−Vr0)−(Vrst−Vth).
Herein, the Vrmp denotes a voltage level of a ramp waveform, and the Vr0 denotes an initial voltage level of the ramp waveform.
When this equation is transformed, the following equation can be obtained:Vin=Vth−(Vrst−Vsig)+(Vrmp−Vr0).That is, the input voltage Vin of the comparing circuit 400 is the sum of the threshold voltage Vth, the electric potential difference—(Vrst−Vsig), in which input voltage is sampled at two points of time, and the variation width of a reference voltage (Vrmp−Vr0). When the difference is zero between the variation width of a reference voltage (Vrmp−Vr0) and the electric potential difference (Vrst−Vsig), the relationship of Vin=Vth (threshold value voltage) is established and the output of the comparing circuit can be reversed.
When the difference is zero between the variation width of a ramp waveform voltage (Vrmp−Vr0) and the electric potential difference (Vrst−Vsig), it means that (Vrmp−Vr0)−(Vrst−Vsig)=0, and it can be expressed as (Vrst−Vsig)=(Vrmp−Vr0).
When the output of the comparing circuit is reversed, a count value of the counter circuit 203 is latched in the digital memory circuit 206. The counter output latched in the digital memory circuit 206 is output from the solid-state image capturing apparatus as digital pixel data of an analog pixel signal.
A reset sampling period Trs denotes a period of time from when the switch 401c is turned on to when it is turned off. A signal sampling period Tss denotes a period of time from when the switch 401b is turned on to when the switch 401a is turned off. In a case where the reset sampling period Trs and the signal sampling period Tss are sufficiently long, the sample hold circuit 4A1 in the column-parallel A/D converter samples a voltage level after the input signal (pixel signal) Vpix is stabilized from the pixel. As a result, it becomes possible to perform an A/D conversion on a difference voltage of a reset voltage and a signal voltage at accurate dark and bright periods.
On the contrary, as illustrated in the timing diagram of FIG. 13, in a case where the reset sampling period Trs and the signal sampling period Tss are both extremely short for the pixel signal Vpix in the A/D converter of the conventional technique, the sampling of the pixel signal Vpix is performed in the sample hold circuit 4A1 while the pixel signal Vpix is not sufficiently settled.
Reference 1: Japanese Laid-Open Publication No. 2000-286706